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INTEGRATED CIRCUITS
DATA SHEET
TDA4671 Picture Signal Improvement (PSI) circuit
Product specification Supersedes data of June 1993 File under Integrated Circuits, IC02 1996 Dec 11
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
FEATURES * Luminance signal delay from 20 to 1100 ns (minimum step 45 ns) * Luminance signal peaking with symmetrical overshoots selectable * Selectable 2.6 or 5 MHz peaking centre frequency and degree of peaking (-3, 0, +3 and +6 dB) * Selectable noise reduction by coring * Handles negative as well as positive colour-difference signals * Selectable Colour Transient Improvement (CTI) to decrease the colour-difference signal transient times to those of the high frequency luminance signals * Selectable 5 or 12 V sandcastle input voltage * All controls selected via the I2C-bus * Timing pulse generation for clamping and delay time control synchronized by sandcastle pulse * Automatic luminance signal delay correction using a control loop * Luminance and colour-difference input signal clamping with coupling capacitor * 4.5 to 8.8 V supply voltage range * Minimum of external components. QUICK REFERENCE DATA SYMBOL VP IP(tot) td(Y) Vi(VBS)(p-p) Vi(CD)(p-p) PARAMETER supply voltage (pins 1 and 5) total supply current Y signal delay time composite Y input signal (peak-to-peak value, pin 16) colour-difference input signal (peak-to-peak value) (R - Y) on pin 3 (R - Y) on pin 7 GY GCD Tamb gain of Y channel gain of colour-difference channel operating ambient temperature - - - - 0 1.05 1.33 -1 0 - 1.48 1.88 - - 70 4.5 31 20 - MIN. 5 41 - 450 TYP. 8.8 52 1130 640 MAX. GENERAL DESCRIPTION
TDA4671
The TDA4671 delays the luminance signal and improves colour-difference signal transients. The luminance signal can also be improved by peaking and noise reduction (coring).
UNIT V mA ns mV
V V dB dB C
ORDERING INFORMATION TYPE NUMBER TDA4671 1996 Dec 11 PACKAGE NAME DIP18 DESCRIPTION plastic dual in-line package; 18 leads (300 mil) 2 VERSION SOT102-1
Product specification
TDA4671
Fig.1 Block diagram.
handbook, full pagewidth
1996 Dec 11
100 nF 2 1 Vref GENERATION Vref I2C-BUS Vref Y delay sandcastle 5 V/12 V Vref CORING 5 MHz
-0.5
sandcastle pulse SDA SCL 100 nF 15 10 9 I2C-BUS RECEIVER CTI on/off coring on/off peaking frequency degree of peaking VP1 = 5 to 8 V
BLOCK DIAGRAM
17
Philips Semiconductors
SANDCASTLE PULSE DETECTOR
BK
BK, H + V DELAY TIME CONTROL
Y 100 ns 90 ns
16
BLACK LEVEL CLAMP
+
CORING 11 100 nF
100 nF
2.6 MHz
Vref control signal
-0.5
5 MHz 2.6 MHz I2C-BUS PEAKING
Picture Signal Improvement (PSI) circuit
3
BLACK LEVEL CLAMP 180 ns
+1
I2C-BUS 90 ns 45 ns 90 ns 100 ns BLACK LEVEL CLAMP
450 ns
180 ns
+
100 nF
13
Vref
TDA4671
analog switch
12
Y
14
100 nF
Vref
-(R - Y)
3
10 nF FULL-WAVE RECTIFIER HIGH-PASS FILTER
BLACK LEVEL CLAMP
4 -(R - Y) I2C-BUS VT comparator 6 -(B - Y) analog switch 8 18 5
MED746
DIFFERENTIATOR
BK FULL-WAVE RECTIFIER
storage capacitors
DIFFERENTIATOR
-(B - Y)
7
10 nF
BLACK LEVEL CLAMP
Vref
VP2 = 5 to 8 V
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
PINNING SYMBOL VP1 CDL Vi(R - Y) Vo(R - Y) VP2 Vo(B - Y) Vi(B - Y) GND2 SDA SCL CCOR VoY CCLP1 CCLP2 Cref ViY SAND GND1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DESCRIPTION positive supply voltage 1 capacitor of delay time control (R - Y) colour-difference input signal (R - Y) colour-difference output signal positive supply voltage 2 (B - Y) colour-difference output signal (B - Y) colour-difference input signal ground 2 (0 V) I2C-bus serial data input/output I2C-bus serial clock input coring capacitor delayed luminance output signal black level clamping capacitor 1 black level clamping capacitor 2 capacitor of reference voltage luminance input signal sandcastle pulse input ground 1 (0 V) Fig.2 Pin configuration.
handbook, halfpage
TDA4671
VP1 1 CDL 2 Vi(R - Y) 3 Vo(R - Y) 4 VP2 5 Vo(B - Y) 6 Vi(B - Y) 7 GND2 8 SDA 9
MED747
18 GND1 17 SAND 16 ViY 15 Cref
TDA4671
14 CCLP2 13 CCLP1 12 VoY 11 CCOR 10 SCL
1996 Dec 11
4
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
FUNCTIONAL DESCRIPTION The TDA4671 contains luminance signal processing and colour-difference signal processing. The luminance signal section comprises a variable, integrated luminance delay line with luminance signal peaking and a noise reduction by coring. The colour-difference section consists of a transient improvement circuit to decrease the rise and fall times of the colour-difference signal transients. All functions and parameters are controlled via the I2C-bus. Y-signal path The video and blanking signal is AC-coupled to the input pin 16. Its black porch is clamped to a DC reference voltage to ensure the correct operating range of the luminance delay stage. The luminance delay line consists of all-pass filter sections with delay times of 45, 90, 100, 180 and 450 ns (see Fig.1). The luminance signal delay is controlled via the I2C-bus in steps of 45 ns in the range of 20 to 1100 ns, this ensures that the maximum delay difference between the luminance and colour-difference signals is 22.5 ns. An automatic luminance delay time adjustment in an internal control loop (with the horizontal frequency as a reference) is used to correct changes in the delay time, due to component tolerances. The control loop is automatically enabled between the burst key pulses of lines 16 (330) and 17 (331) during the vertical blanking interval. The control voltage is stored in capacitor CDL connected to pin 2. The peaking section is using a transversal filter circuit with selectable centre frequencies of 2.6 and 5.0 MHz. It provides selectable degrees of peaking of -3, 0, +3 and +6 dB and noise reduction by coring, which attenuates the high-frequency noise introduced by peaking.
TDA4671
The output buffer stage ensures a low-ohmic VBS output signal on pin 12 (<160 ). The gain of the luminance signal path from pin 16 to pin 12 is unity. An oscillation signal of the delay time control loop is present on output pin 12 instead of the VBS signal. It is present during the vertical blanking interval of the burst key pulses in lines 16 (330) to 18 (332). This sync should not be applied for synchronization. Colour-difference signal paths The colour-difference input signals (on pins 3 and 7) are clamped to a reference voltage. Each colour-difference signal is fed to a transient detector and to an analog signal switch with an attached voltage storage stage. The transient detectors consist of differentiators and full-wave rectifiers. The output voltages of both transient detectors are added and then compared. The comparator controls both following analog signal switches simultaneously. The analog signal switches are in open position at a certain value of transient time; the held value (held by capacitors) is then applied to the outputs. The switches close to rapidly accept the actual signal levels at the end of these transients. The improved transient time is approximately 100 ns long independent of the input transient time. Colour-difference paths are independent of the input signal polarity and have a nominal unity gain. The CTI functions are switched on and off via the I2C-bus.
1996 Dec 11
5
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
TDA4671
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). VP1 and VP2 as well as GND1 and GND2 connected together. SYMBOL VP1 VP2 Ptot Tstg Tamb VESD PARAMETER supply voltage (pin 1) supply voltage (pin 5) total power dissipation storage temperature operating ambient temperature electrostatic handling for pins 9 and 10 for other pins Note 1. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 82 UNIT K/W note 1 - - - +300 -500 500 V V V CONDITIONS 0 0 0 -25 0 MIN. MAX. 8.8 8.8 0.97 +150 70 V V W C C UNIT
CHARACTERISTICS VP1 = VP2 = 5 V; nominal video amplitude VVB = 315 mV; tH = 64 s; tBK = 4 s (burst key); Tamb = 25 C and measurements taken in Fig.4; unless otherwise specified. SYMBOL VP1 VP2 IP(tot) Y-signal path Vi(Y)(p-p) V16 I16 R16 C16 td(Y)(max) td(Y)(min) VBS input signal on pin 16 (peak-to-peak value) black level clamping voltage input current input resistance input capacitance maximum Y delay time minimum Y delay time set via I2C-bus set via I2C-bus during clamping outside clamping outside clamping - - 95 - 5 - 1070 - 450 3.1 - - - 3 1100 20 640 - 190 0.1 - 10 1130 - mV V A A M pF ns ns PARAMETER supply voltage (pin 1) supply voltage (pin 5) total supply current CONDITIONS MIN. 4.5 4.5 31 TYP. 5 5 41 MAX. 8.8 8.8 52 UNIT V V mA
1996 Dec 11
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Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
TDA4671
SYMBOL td(Y)
PARAMETER minimum delay step group delay time difference delay time difference between Y and colour-difference signals set via
CONDITIONS I2C-bus f = 0.5 to 5 MHz; maximum delay Y delay; CTI and peaking off Vo/Vi; f = 500 kHz; maximum delay source current sink current maximum delay f = 0.5 to 3 MHz f = 0.5 to 5 MHz
MIN. 40 - 70 185 -2
TYP. 45 0 100 215 -1
MAX. 50 25 130 245 0
UNIT ns ns ns ns dB
td(peak) GY
minimum delay time for peaking VBS signal gain measured on output pin 12 (composite signal, peak-to-peak value) output current (emitter-follower with constant current source) output resistance frequency response for
I12 R12 fres
-1 0.4 - -2 -4 0.85 0.60
- - - -1 -3 - -
- - 160 0 -1 - -
mA mA dB dB - -
LIN
signal linearity for video contents of 315 mV (p-p) video contents of 450 mV (p-p)
min/max; VVBS = 450 mV (p-p) VVBS = 640 mV (p-p)
Luminance peaking, selected via I2C-bus fpeak Vpeak peaking frequency peaking amplitude for grade of peaking (fC amplitude over 0.5 MHz amplitude) selectable values - - - - limitation of peaking (positive amplitude of correction signal referred to 315 mV) Vn(rms) COR noise voltage on pin 12 (RMS value) coring of peaking (coring part referred to 315 mV) without peaking; f = 0 to 5 MHz COR-bit = 1 - -3 0 +3 +6 20 - - - - - dB dB dB dB % fC1; LCF-bit = 0 fC2; LCF-bit = 1 4.5 2.3 5 2.6 5.5 2.9 MHz MHz
- -
- 20
1 -
mV %
1996 Dec 11
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Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
TDA4671
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Colour-difference paths measured with transient times tr = tf = 1 s; tp H 1 s; Vi = 1.33 V (p-p) on pins 3 and 7 and with burst key pulse tBK = 4 s Vi(CD)(p-p) (R - Y) input signal (peak-to-peak value; pin 3) (B - Y) input signal (peak-to-peak value; pin 7) input transient sensitivity V3,7 I3,7 C3,7 V4,6 V4,6 Vspike I4,6 R4,6 Gv Gv LIN internal clamping voltage level input current input capacitance DC output voltage output offset voltage spurious spike signals on pins 4 and 6 output current (emitter-follower with constant current source) output resistance signal gain in each path gain difference -(R - Y)/-(B - Y) signal linearity for nominal signal +3 dB signal Vo min/max; Vi = 1.33 V (p-p) Vi = 1.88 V (p-p) 0.90 0.65 -1.5 - - - - - - - - dB Vo/Vi RS 300 ; note 1 RS 300 ; note 1 source current sink current outside clamping during clamping 75% colour bar 75% colour bar V3,7/t - - 0.22 - - 100 - - - - -1 0.4 - -1 - during and after storage time - 1.05 1.33 - 2.45 - - 6 2 - - - - - - 0 0 1.48 1.88 - - 1 190 12 - 5 18 30 - - 100 +1 0.3 V V V/s V A A pF V mV mV mV mA mA dB dB
signal reduction at higher frequency signal with tp H = 50 ns; (output signal ratio Vi/Vo) tr = tf = 1 s
Sandcastle pulse, input voltage selectable via I2C-bus V17 input voltage threshold for H and V sync input voltage threshold for burst input voltage threshold for H and V sync input voltage threshold for burst R17 C17 tBK td np input resistance input capacitance burst key pulse width leading edge delay for clamping pulse referred to tBK SC5-bit = 0 (12 V) SC5-bit = 0 (12 V) SC5-bit = 1 (5 V) SC5-bit = 1 (5 V) +12 V input level +5 V input level 1.1 5.5 1.1 3.0 30 15 - 3.0 - 4 1.5 6.5 1.5 3.5 40 20 4 4.0 1 - 1.9 7.5 1.9 4.0 50 25 8 4.6 - 31 V V V V k k pF s s -
number of required burst key pulses note 2 vertical blanking interval
1996 Dec 11
8
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
TDA4671
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2C-bus control, SDA and SCL VIH VIL I9,10 Vo(ACK) Io(ACK) Notes 1. Crosstalk on output, measured in the unused channel when the other channel is provided with a nominal input signal (CTI active). 2. A number of more than 31 burst key pulses repeats the counter cycle of delay time control. I2C-BUS FORMAT S(1) Notes 1. S = START condition. 2. SLAVE ADDRESS = 1000 100X. 3. ACK = acknowledge, generated by the slave. 4. SUBADDRESS = subaddress byte, see Table 1. 5. DATA = data byte, see Table 1. 6. P = STOP condition. 7. X = read/write control bit. X = 0, order to write (the circuit is slave receiver). X = 1, order to read (the circuit is slave transmitter). If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed. Table 1 I2C-bus transmission; see Table 2 DATA FUNCTION Y delay/CTI/SC SUBADDRESS D7 00010000 0 COR Peaking and coring 00010001 D6 SC5 PEAK D5 CTI LCF D4 DL4 0 D3 DL3 0 D2 DL2 0 D1 DL1 D0 DL0 SLAVE ADDRESS(2) ACK(3) SUBADDRESS(4) ACK(3) DATA(5) P(6) HIGH level input voltage on pins 9 and 10 LOW level input voltage input current output voltage at acknowledge on pin 9 output current at acknowledge on pin 9 Io(ACK) = 3 mA sink current 3 0 - - 3 - - - - - 5 1.5 10 0.4 - V V A V mA
PCON1 PCON0
1996 Dec 11
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Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
Table 2 Function of the bits FUNCTION set delay in luminance channel LOGIC 1 45 ns 90 ns 180 ns 180 ns 450 ns set colour transient improvement select sandcastle pulse voltage set peaking frequency response set peaking delay set coring control set peaking amplification Peaking amplification PCON0 0 1 0 1 GRADE OF PEAKING (dB) -3 0 +3 +6 active +5 V 2.6 MHz active active
TDA4671
DATA DL0 DL1 DL2 DL3 DL4 CTI SC5 LCF PEAK COR PCONx Table 3
LOGIC 0 0 ns 0 ns 0 ns 0 ns 0 ns inactive +12 V 5.0 MHz inactive inactive
see Table 3
PCON1 0 0 1 1
Remarks to the subaddress bytes Subaddresses 00H to 0FH are reserved for colour decoders and RGB processors. Subaddresses 10 and 11 only are acknowledged. General call address is not acknowledged. Power-on-reset: D7 to D1 bits of data bytes are set to logic 0, D0 bit is set to logic 1.
1996 Dec 11
10
Product specification
TDA4671
Fig.3 Internal circuit.
handbook, full pagewidth
1996 Dec 11
Cref CCLP 14 13 12 CCLP 15 Y output
SC
Y input
17
16
Philips Semiconductors
INTERNAL CIRCUITRY
+ + + +
+
11
CCOR
GND
18
+
all input and output pins without pins 9 and 10
TDA4671
+
Picture Signal Improvement (PSI) circuit
11
+ + +
10 SCL
VP
1
+
2 CD output
3
4
5 VP
6 CD output
7 CD input
8 GND
9 SDA
MED749
CDL
CD input
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
TEST AND APPLICATION INFORMATION
TDA4671
handbook, full pagewidth
SDA I2C-bus SCL CCOR 0.1 F (VBS) VoY 10 9 GND2 Vi(B - Y) 10 nF Vo(B - Y) VP2 Vo(R - Y) Vi(R - Y) CDL VP1 10 nF 0.1 F +5 V 47 F SDA
11
8
12
7
CCLP1 0.1 F CCLP2 0.1 F Cref 0.1 F (VBS) sandcastle pulse input ViY 0.1 F SAND
13
6
14
TDA4671
5
15
4
16
3
17 GND1
2
18
1
MED748
15 VB
Fig.4 Test and application circuit.
1996 Dec 11
12
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
PACKAGE OUTLINE DIP18: plastic dual in-line package; 18 leads (300 mil)
TDA4671
SOT102-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 18 10 b2 MH wM (e 1)
pin 1 index E
1
9
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 3.7 0.15 b 1.40 1.14 0.055 0.044 b1 0.53 0.38 0.021 0.015 b2 1.40 1.14 0.055 0.044 c 0.32 0.23 0.013 0.009 D (1) 21.8 21.4 0.86 0.84 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.9 3.4 0.15 0.13 ME 8.25 7.80 0.32 0.31 MH 9.5 8.3 0.37 0.33 w 0.254 0.01 Z (1) max. 0.85 0.033
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT102-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 93-10-14 95-01-23
1996 Dec 11
13
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA4671
with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Dec 11
14
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
NOTES
TDA4671
1996 Dec 11
15
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/03/pp16
Date of release: 1996 Dec 11
Document order number:
9397 750 01472

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